# 1 "FWlib/apt32f102_ept.c"
# 1 "E:\\APT_Landscape_mode\\APT32F1023_New\\Source//"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "FWlib/apt32f102_ept.c"
# 19 "FWlib/apt32f102_ept.c"
# 1 "include/apt32f102_ept.h" 1
# 23 "include/apt32f102_ept.h"
# 1 "include/apt32f102.h" 1
# 23 "include/apt32f102.h"
# 1 "include/apt32f102_types_local.h" 1
# 63 "include/apt32f102_types_local.h"
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;


typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;


typedef float F32_T;
typedef double F64_T;


typedef U8_T B_T;
# 100 "include/apt32f102_types_local.h"
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;




typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;




typedef unsigned char UINT8;
typedef signed char SINT8;


typedef unsigned short UINT16;
typedef signed short SINT16;


typedef unsigned long UINT32;
typedef signed long SINT32;

typedef void VOID;
typedef signed char CHAR;
typedef unsigned char BOOL;
typedef signed long TIME_T;

typedef float SINGLE;



typedef double DOUBLE;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
} REG8;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
  unsigned bit8 : 1;
  unsigned bit9 : 1;
  unsigned bit10: 1;
  unsigned bit11: 1;
  unsigned bit12: 1;
  unsigned bit13: 1;
  unsigned bit14: 1;
  unsigned bit15: 1;
} REG16;






typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
# 24 "include/apt32f102.h" 2
# 1 "include/apt32f102_ck801.h" 1
# 85 "include/apt32f102_ck801.h"
typedef enum IRQn
{

        ISR_Restart = -32,
        ISR_Misaligned_Access = -31,
        ISR_Access_Error = -30,
        ISR_Divided_By_Zero = -29,
        ISR_Illegal = -28,
        ISR_Privlege_Violation = -27,
        ISR_Trace_Exection = -26,
        ISR_Breakpoint_Exception = -25,
        ISR_Unrecoverable_Error = -24,
        ISR_Idly4_Error = -23,
        ISR_Auto_INT = -22,
        ISR_Auto_FINT = -21,
        ISR_Reserved_HAI = -20,
        ISR_Reserved_FP = -19,
        ISR_TLB_Ins_Empty = -18,
        ISR_TLB_Data_Empty = -17,

        INTC_CORETIM_IRQn = 0,
        INTC_TIME1_IRQn = 1,
        INTC_UART0_IRQn = 2,
        INTC_GPIOA2_IRQn = 8,
} IRQn_Type;


void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);

void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
# 25 "include/apt32f102.h" 2




typedef struct {
 volatile unsigned int ReservedA[4];
 volatile unsigned int CORET_CSR;
 volatile unsigned int CORET_RVR;
 volatile unsigned int CORET_CVR;
 volatile unsigned int CORET_CALIB;
 volatile unsigned int ReservedB[56];
 volatile unsigned int ISER;
 volatile unsigned int ReservedC[15];
 volatile unsigned int IWER;
 volatile unsigned int ReservedD[15];
 volatile unsigned int ICER;
 volatile unsigned int ReservedE[15];
 volatile unsigned int IWDR;
 volatile unsigned int ReservedF[15];
 volatile unsigned int ISPR;
 volatile unsigned int ReservedG[31];
 volatile unsigned int ICPR;
 volatile unsigned int ReservedH[31];
 volatile unsigned int IABR;
 volatile unsigned int ReservedI[63];
 volatile unsigned int IPR[8];
 volatile unsigned int ReservedJ[504];
 volatile unsigned int ISR;
 volatile unsigned int IPTR;
} CSP_CK801_T;



typedef volatile struct {
 volatile unsigned int IDR ;
 volatile unsigned int CEDR ;
 volatile unsigned int SRR ;
 volatile unsigned int CMR ;
 volatile unsigned int CR ;
 volatile unsigned int MR ;
 volatile unsigned int FM_ADDR ;
 volatile unsigned int Reserved ;
 volatile unsigned int KR ;
 volatile unsigned int IMCR ;
 volatile unsigned int RISR ;
 volatile unsigned int MISR ;
 volatile unsigned int ICR ;
} CSP_IFC_T ;



typedef volatile struct {
 volatile unsigned int IDCCR;
 volatile unsigned int GCER;
 volatile unsigned int GCDR;
 volatile unsigned int GCSR;
 volatile unsigned int CKST;
 volatile unsigned int RAMCHK;
 volatile unsigned int EFLCHK;
 volatile unsigned int SCLKCR;
 volatile unsigned int PCLKCR;
 volatile unsigned int _RSVD0;
 volatile unsigned int PCER0;
 volatile unsigned int PCDR0;
 volatile unsigned int PCSR0;
 volatile unsigned int PCER1;
 volatile unsigned int PCDR1;
 volatile unsigned int PCSR1;
 volatile unsigned int OSTR;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int LVDCR;
 volatile unsigned int CLCR;
 volatile unsigned int PWRCR;
 volatile unsigned int PWRKEY;
 volatile unsigned int _RSVD3;
 volatile unsigned int _RSVD4;
 volatile unsigned int OPT1;
 volatile unsigned int OPT0;
 volatile unsigned int WKCR;
 volatile unsigned int _RSVD5;
 volatile unsigned int IMER;
 volatile unsigned int IMDR;
 volatile unsigned int IMCR;
 volatile unsigned int IAR;
 volatile unsigned int ICR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int RSR;
 volatile unsigned int EXIRT;
 volatile unsigned int EXIFT;
 volatile unsigned int EXIER;
 volatile unsigned int EXIDR;
 volatile unsigned int EXIMR;
 volatile unsigned int EXIAR;
 volatile unsigned int EXICR;
 volatile unsigned int EXIRS;
 volatile unsigned int IWDCR;
 volatile unsigned int IWDCNT;
 volatile unsigned int IWDEDR;
 volatile unsigned int IOMAP0;
 volatile unsigned int IOMAP1;
 volatile unsigned int CINF0;
 volatile unsigned int CINF1;
 volatile unsigned int FINF0;
 volatile unsigned int FINF1;
 volatile unsigned int FINF2;
 volatile unsigned int _RSVD6;
 volatile unsigned int ERRINF;
 volatile unsigned int UID0 ;
 volatile unsigned int UID1 ;
 volatile unsigned int UID2 ;
 volatile unsigned int PWROPT;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVSWF;
 volatile unsigned int UREG0;
 volatile unsigned int UREG1;
 volatile unsigned int UREG2;
 volatile unsigned int UREG3;
} CSP_SYSCON_T;



 typedef volatile struct
 {
    volatile unsigned int EN;
    volatile unsigned int SWTRG;
    volatile unsigned int CH0CON0;
    volatile unsigned int CH0CON1;
    volatile unsigned int CH1CON0;
    volatile unsigned int CH1CON1;
    volatile unsigned int CH2CON0;
    volatile unsigned int CH2CON1;
 volatile unsigned int _RSVD0;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int _RSVD3;
    volatile unsigned int CH3CON;
 volatile unsigned int CH4CON;
 volatile unsigned int CH5CON;
 volatile unsigned int CH6CON;
 volatile unsigned int CH7CON;
 } CSP_ETCB_T, *CSP_ETCB_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CCR;
   volatile unsigned int TCH_CON0;
   volatile unsigned int TCH_CON1;
   volatile unsigned int TCH_SCCR;
   volatile unsigned int TCH_SENPRD;
   volatile unsigned int TCH_VALBUF;
   volatile unsigned int TCH_SENCNT;
   volatile unsigned int TCH_TCHCNT;
   volatile unsigned int TCH_THR;
   volatile unsigned int Reserved0;
   volatile unsigned int TCH_RISR;
   volatile unsigned int TCH_IER;
   volatile unsigned int TCH_ICR;
   volatile unsigned int TCH_RWSR;
   volatile unsigned int TCH_OVW_THR;
   volatile unsigned int TCH_OVF;
   volatile unsigned int TCH_OVT;
   volatile unsigned int TCH_SYNCR;
   volatile unsigned int TCH_EVTRG;
   volatile unsigned int TCH_EVPS;
   volatile unsigned int TCH_EVSWF;
} CSP_TKEY_T, *CSP_TKEY_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CHVAL[18];
   volatile unsigned int TCH_SEQCON[18];
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;



 typedef volatile struct
 {
    volatile unsigned int ECR;
    volatile unsigned int DCR;
    volatile unsigned int PMSR;
    volatile unsigned int Reserved0;
    volatile unsigned int CR;
    volatile unsigned int MR;
    volatile unsigned int SHR;
    volatile unsigned int CSR;
    volatile unsigned int SR;
    volatile unsigned int IER;
    volatile unsigned int IDR;
    volatile unsigned int IMR;
    volatile unsigned int SEQ[16];
    volatile unsigned int PRI;
    volatile unsigned int TDL0;
    volatile unsigned int TDL1;
    volatile unsigned int SYNCR;
    volatile unsigned int Reserved1;
    volatile unsigned int Reserved2;
    volatile unsigned int EVTRG;
    volatile unsigned int EVPS;
    volatile unsigned int EVSWF;
    volatile unsigned int ReservedD[27];
    volatile unsigned int DR[16];
    volatile unsigned int CMP0;
    volatile unsigned int CMP1;
 volatile unsigned int DRMASK;
 } CSP_ADC12_T, *CSP_ADC12_PTR;



 typedef volatile struct
 {
    volatile unsigned int CONLR;
    volatile unsigned int CONHR;
    volatile unsigned int WODR;
    volatile unsigned int SODR;
    volatile unsigned int CODR;
    volatile unsigned int ODSR;
    volatile unsigned int PSDR;
    volatile unsigned int FLTEN;
    volatile unsigned int PUDR;
    volatile unsigned int DSCR;
    volatile unsigned int OMCR;
    volatile unsigned int IECR;
 volatile unsigned int IEER;
 volatile unsigned int IEDR;
 } CSP_GPIO_T, *CSP_GPIO_PTR;

 typedef volatile struct
 {
 volatile unsigned int IGRPL;
    volatile unsigned int IGRPH;
 volatile unsigned int IGREX;
    volatile unsigned int IO_CLKEN;
 } CSP_IGRP_T, *CSP_IGRP_PTR;



 typedef volatile struct
 {
    volatile unsigned int DATA;
    volatile unsigned int SR;
    volatile unsigned int CTRL;
    volatile unsigned int ISR;
    volatile unsigned int BRDIV;
    volatile unsigned int ReservedA[20];
 } CSP_UART_T, *CSP_UART_PTR;



typedef struct
{
 volatile unsigned int CR0;
 volatile unsigned int CR1;
 volatile unsigned int DR;
 volatile unsigned int SR;
 volatile unsigned int CPSR;
 volatile unsigned int IMSCR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int ICR;
} CSP_SSP_T, *CSP_SSP_PTR;



typedef struct
{
 volatile unsigned int CR;
 volatile unsigned int TXCR0;
 volatile unsigned int TXCR1;
 volatile unsigned int TXBUF;
 volatile unsigned int RXCR0;
 volatile unsigned int RXCR1;
 volatile unsigned int RXCR2;
 volatile unsigned int RXBUF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;



 typedef volatile struct
 {
    unsigned int CR;
    unsigned int TADDR;
    unsigned int SADDR;
    unsigned int ReservedD;
    unsigned int DATA_CMD;
    unsigned int SS_SCLH;
    unsigned int SS_SCLL;
    unsigned int FS_SCLH;
    unsigned int FS_SCLL;
    unsigned int ReservedA;
    unsigned int ReservedC;
    unsigned int RX_FLSEL;
    unsigned int TX_FLSEL;
    unsigned int RX_FL;
    unsigned int TX_FL;
    unsigned int ENABLE;
    unsigned int STATUS;
    unsigned int ReservedB;
    unsigned int SDA_TSETUP;
    unsigned int SDA_THOLD;
    unsigned int SPKLEN;

    unsigned int ReservedE;
 unsigned int MISR;
    unsigned int IMSCR;
    unsigned int RISR;
    unsigned int ICR;
    unsigned int ReservedF;
    unsigned int SCL_TOUT;
    unsigned int SDA_TOUT;
    unsigned int TX_ABRT;
    unsigned int GCALL;
    unsigned int NACK;
 } CSP_I2C_T, *CSP_I2C_PTR;



 typedef struct
 {
    volatile unsigned int CADATAH;
    volatile unsigned int CADATAL;
    volatile unsigned int CACON;
    volatile unsigned int INTMASK;
 } CSP_CA_T, *CSP_CA_PTR;



 typedef struct
 {
 volatile unsigned int CEDR;
 volatile unsigned int RSSR;
 volatile unsigned int PSCR;
 volatile unsigned int CR;
 volatile unsigned int SYNCR;
 volatile unsigned int GLDCR;
 volatile unsigned int GLDCFG;
 volatile unsigned int GLDCR2;
 volatile unsigned int Reserved0;
 volatile unsigned int PRDR;
 volatile unsigned int Reserved1;
 volatile unsigned int CMPA;
 volatile unsigned int CMPB;
 volatile unsigned int Reserved2;
 volatile unsigned int Reserved3;
 volatile unsigned int CMPLDR;
 volatile unsigned int CNT;
 volatile unsigned int AQLDR;
 volatile unsigned int AQCRA;
 volatile unsigned int AQCRB;
 volatile unsigned int Reserved4;
 volatile unsigned int Reserved5;
 volatile unsigned int Reserved6;
 volatile unsigned int AQOSF;
 volatile unsigned int AQCSF;
 volatile unsigned int Reserved7;
 volatile unsigned int Reserved8;
 volatile unsigned int Reserved9;
 volatile unsigned int Reserved10;
 volatile unsigned int Reserved11;
 volatile unsigned int Reserved12;
 volatile unsigned int Reserved13;
 volatile unsigned int Reserved14;
 volatile unsigned int Reserved15;
 volatile unsigned int Reserved16;
 volatile unsigned int Reserved17;
 volatile unsigned int Reserved18;
 volatile unsigned int Reserved19;
 volatile unsigned int Reserved20;
 volatile unsigned int Reserved21;
 volatile unsigned int Reserved22;
 volatile unsigned int Reserved23;
 volatile unsigned int Reserved24;
 volatile unsigned int Reserved25;
 volatile unsigned int Reserved26;
 volatile unsigned int Reserved27;
 volatile unsigned int TRGFTCR;
 volatile unsigned int TRGFTWR;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVCNTINIT;
 volatile unsigned int EVSWF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
 volatile unsigned int REGLINK;

 }CSP_GPT_T,*CSP_GPT_PTR;



 typedef struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int GLDCR;
   volatile unsigned int GLDCFG;
   volatile unsigned int GLDCR2;
   volatile unsigned int HRCFG;
   volatile unsigned int PRDR;
   volatile unsigned int PHSR;
   volatile unsigned int CMPA;
   volatile unsigned int CMPB;
   volatile unsigned int CMPC;
   volatile unsigned int CMPD;
   volatile unsigned int CMPLDR;
   volatile unsigned int CNT;
   volatile unsigned int AQLDR;
   volatile unsigned int AQCRA;
   volatile unsigned int AQCRB;
   volatile unsigned int AQCRC;
   volatile unsigned int AQCRD;
   volatile unsigned int AQTSCR;
   volatile unsigned int AQOSF;
   volatile unsigned int AQCSF;
   volatile unsigned int DBLDR;
   volatile unsigned int DBCR;
   volatile unsigned int DPSCR;
   volatile unsigned int DBDTR;
   volatile unsigned int DBDTF;
   volatile unsigned int CPCR;
   volatile unsigned int EMSRC;
   volatile unsigned int EMSRC2;
   volatile unsigned int EMPOL;
   volatile unsigned int EMECR;
   volatile unsigned int EMOSR;
   volatile unsigned int Reserved;
   volatile unsigned int EMSLSR;
   volatile unsigned int EMSLCLR;
   volatile unsigned int EMHLSR;
   volatile unsigned int EMHLCLR;
   volatile unsigned int EMFRCR;
   volatile unsigned int EMRISR;
   volatile unsigned int EMMISR;
   volatile unsigned int EMIMCR;
   volatile unsigned int EMICR;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINIT;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
   volatile unsigned int REGLINK;
   volatile unsigned int REGLINK2;
   volatile unsigned int REGPROT;
} CSP_EPT_T, *CSP_EPT_PTR;



 typedef volatile struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
} CSP_LPT_T, *CSP_LPT_PTR;



 typedef struct
 {
   volatile unsigned int RSSR;
   volatile unsigned int CR;
   volatile unsigned int PSCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINTI;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
} CSP_BT_T, *CSP_BT_PTR;



typedef struct
{
   volatile unsigned int IDR;
   volatile unsigned int CEDR;
   volatile unsigned int SRR;
   volatile unsigned int CR;
   volatile unsigned int SEED;
   volatile unsigned int DATAIN;
   volatile unsigned int DATAOUT;

} CSP_CRC_T, *CSP_CRC_PTR;



 typedef struct
 {
   volatile unsigned int TIMR;
   volatile unsigned int DATR;
   volatile unsigned int CR;
   volatile unsigned int CCR;
   volatile unsigned int ALRAR;
   volatile unsigned int ALRBR;
   volatile unsigned int SSR;
   volatile unsigned int CAL;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
   volatile unsigned int KEY;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
} CSP_RTC_T, *CSP_RTC_PTR;




 typedef struct
 {
  volatile unsigned int CR;
  volatile unsigned int CFGR;
  volatile unsigned int RISR;
  volatile unsigned int MISR;
  volatile unsigned int IMCR;
  volatile unsigned int ICR;
 }CSP_WWDT_T,*CSP_WWDT_PTR;



 typedef struct
 {
  volatile S32_T DIVIDENT;
  volatile S32_T DIVISOR;
  volatile S32_T QUOTIENT;
  volatile S32_T REMAIN;
  volatile unsigned int CR;
 }CSP_HWD_T,*CSP_HWD_PTR;
# 691 "include/apt32f102.h"
extern CSP_CK801_T *CK801 ;

extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;

extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;

extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;

extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;

extern CSP_GPT_T *GPT0 ;

extern CSP_EPT_T *EPT0 ;

extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;

extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;


void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));

void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));

extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
# 24 "include/apt32f102_ept.h" 2






typedef enum
{
 EPT_IO_CHAX = 0,
 EPT_IO_CHAY = 1,
 EPT_IO_CHBX = 2,
 EPT_IO_CHBY = 3,
 EPT_IO_CHCX = 4,
 EPT_IO_CHCY = 5,
 EPT_IO_CHD = 6,
 EPT_IO_EPI = 7
}EPT_IO_Mode_Type;



typedef enum
{
 IO_NUM_PA07 = 0X10,
 IO_NUM_PA10 = 0X11,
 IO_NUM_PA15 = 0X12,
 IO_NUM_PB03 = 0X13,
 IO_NUM_PB05 = 0X14,
 IO_NUM_PA12 = 0X15,
 IO_NUM_PB02 = 0X16,
 IO_NUM_PA11 = 0X17,
 IO_NUM_PA14 = 0X18,
 IO_NUM_PB04 = 0X19,
 IO_NUM_PA05 = 0X1A,
 IO_NUM_PA08 = 0X1B,
 IO_NUM_PA03 = 0X1C,
 IO_NUM_PB00 = 0X1D,
 IO_NUM_PA04 = 0X1E,
 IO_NUM_PA09 = 0X1F,
 IO_NUM_PA013 = 0X20
}EPT_IO_NUM_Type;



typedef enum
{
 EPT_Selecte_PCLK = 0<<3,
 EPT_Selecte_SYNCUSR3 = 1<<3
}EPT_TCLK_Selecte_Type;



typedef enum
{
 EPT_CGSRC_TIN_BT0OUT = 0,
 EPT_CGSRC_TIN_BT1OUT = 1,
 EPT_CGSRC_CHAX = 2,
 EPT_CGSRC_CHBX = 3,
 EPT_CGSRC_DIS = 4
}EPT_CGSRC_TIN_Selecte_Type;

typedef enum
{
 EPT_BURST_ENABLE = 1<<9,
 EPT_BURST_DIABLE = 0<<9
}EPT_BURST_CMD_Type;



typedef enum
{
 EPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)),
 EPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)),
 EPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0))
}EPT_CNTMD_SELECTE_Type;



typedef enum
{
 EPT_OPM_Once = ((CSP_REGISTER_T)(0x01ul << 6)),
 EPT_OPM_Continue = ((CSP_REGISTER_T)(0x00ul << 6))
}EPT_OPM_SELECTE_Type;



typedef enum
{
 EPT_CAP_EN = ((CSP_REGISTER_T)(0x01ul << 8)),
 EPT_CAP_DIS = ((CSP_REGISTER_T)(0x00ul << 8))
}EPT_CAPLDEN_CMD_Type;




typedef enum
{
 EPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)),
 EPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20))
}EPT_CAPMD_SELECTE_Type;




typedef enum
{
 EPT_LDARST_EN = ((CSP_REGISTER_T)(0x00ul << 23)),
 EPT_LDARST_DIS = ((CSP_REGISTER_T)(0x01ul << 23))
}EPT_LOAD_CMPA_RST_CMD_Type;



typedef enum
{
 EPT_LDBRST_EN = ((CSP_REGISTER_T)(0x00ul << 24)),
 EPT_LDBRST_DIS = ((CSP_REGISTER_T)(0x01ul << 24))
}EPT_LOAD_CMPB_RST_CMD_Type;



typedef enum
{
 EPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)),
 EPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25))
}EPT_LOAD_CMPC_RST_CMD_Type;



typedef enum
{
 EPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)),
 EPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26))
}EPT_LOAD_CMPD_RST_CMD_Type;



typedef enum
{
 EPT_FLT_DIS = ((CSP_REGISTER_T)(0x00ul << 10)),
 EPT_FLT_EN = ((CSP_REGISTER_T)(0x01ul << 10))
}EPT_FLT_CMD_Type;



typedef enum
{
 EPT_FLT_Bypass = ((CSP_REGISTER_T)(0x00ul << 13)),
 EPT_FLT_2 = ((CSP_REGISTER_T)(0x01ul << 13)),
 EPT_FLT_3 = ((CSP_REGISTER_T)(0x02ul << 13)),
 EPT_FLT_4 = ((CSP_REGISTER_T)(0x03ul << 13)),
 EPT_FLT_6 = ((CSP_REGISTER_T)(0x04ul << 13)),
 EPT_FLT_8 = ((CSP_REGISTER_T)(0x05ul << 13)),
 EPT_FLT_16 = ((CSP_REGISTER_T)(0x06ul << 13)),
 EPT_FLT_32 = ((CSP_REGISTER_T)(0x07ul << 13))
}EPT_FLT_CGFLT_Type;



typedef enum
{
 EPT_Triggle_Continue = ((CSP_REGISTER_T)(0x00ul << 8)),
 EPT_Triggle_Once = ((CSP_REGISTER_T)(0x01ul << 8))
}EPT_Triggle_Mode_Type;



typedef enum
{
 EPT_REARM_SYNCEN0 = ((CSP_REGISTER_T)(0x01ul << 16)),
 EPT_REARM_SYNCEN1 = ((CSP_REGISTER_T)(0x02ul << 16)),
 EPT_REARM_SYNCEN2 = ((CSP_REGISTER_T)(0x04ul << 16)),
 EPT_REARM_SYNCEN3 = ((CSP_REGISTER_T)(0x08ul << 16)),
 EPT_REARM_SYNCEN4 = ((CSP_REGISTER_T)(0x10ul << 16)),
 EPT_REARM_SYNCEN5 = ((CSP_REGISTER_T)(0x20ul << 16))
}EPT_REARMX_Type;



typedef enum
{
 EPT_REARM_Selected_DIS = ((CSP_REGISTER_T)(0x00ul << 30)),
 EPT_REARM_Selected_ZRO_AUTO = ((CSP_REGISTER_T)(0x01ul << 30)),
 EPT_REARM_Selected_PRD_AUTO = ((CSP_REGISTER_T)(0x02ul << 30)),
 EPT_REARM_Selected_ZRO_PRD_AUTO = ((CSP_REGISTER_T)(0x03ul << 30))
}EPT_REARM_MODE_Type;



typedef enum
{
 EPT_SYNCUSR0_REARMTrig_DIS = ((CSP_REGISTER_T)(0x00ul << 22)),
 EPT_SYNCUSR0_REARMTrig_T1 = ((CSP_REGISTER_T)(0x01ul << 22)),
 EPT_SYNCUSR0_REARMTrig_T2 = ((CSP_REGISTER_T)(0x02ul << 22)),
 EPT_SYNCUSR0_REARMTrig_T1T2 = ((CSP_REGISTER_T)(0x03ul << 22))
}EPT_SYNCUSR0_REARMTrig_Selecte_Type;



typedef enum
{
 EPT_TRGSRC0_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 24)),
 EPT_TRGSRC0_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 24))
}EPT_TRGSRC0_ExtSync_Selected_Type;



typedef enum
{
 EPT_TRGSRC1_ExtSync_SYNCUSR0 = ((CSP_REGISTER_T)(0x00ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR1 = ((CSP_REGISTER_T)(0x01ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR2 = ((CSP_REGISTER_T)(0x02ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR3 = ((CSP_REGISTER_T)(0x03ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR4 = ((CSP_REGISTER_T)(0x04ul << 27)),
 EPT_TRGSRC1_ExtSync_SYNCUSR5 = ((CSP_REGISTER_T)(0x05ul << 27))
}EPT_TRGSRC1_ExtSync_Selected_Type;



typedef enum
{
 EPT_PHSEN_DIS = ((CSP_REGISTER_T)(0x00ul << 8)),
 EPT_PHSEN_EN = ((CSP_REGISTER_T)(0x01ul << 8))
}EPT_PHSEN_CMD_Type;



typedef enum
{
 EPT_PHSDIR_increase = ((CSP_REGISTER_T)(0x01ul << 31)),
 EPT_PHSEN_decrease = ((CSP_REGISTER_T)(0x00ul << 31))
}EPT_PHSDIR_Type;



typedef enum
{
 EPT_GLDMD_Selecte_ZRO = ((CSP_REGISTER_T)(0x00ul << 1)),
 EPT_GLDMD_Selecte_PRD = ((CSP_REGISTER_T)(0x01ul << 1)),
 EPT_GLDMD_Selecte_ZRO_PRD = ((CSP_REGISTER_T)(0x02ul << 1)),
 EPT_GLDMD_Selecte_ZRO_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x03ul << 1)),
 EPT_GLDMD_Selecte_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x04ul << 1)),
 EPT_GLDMD_Selecte_ZRO_PRD_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x05ul << 1)),
 EPT_GLDMD_Selecte_SW = ((CSP_REGISTER_T)(0x0Ful << 1))
}EPT_GLDMD_Selecte_Type;



typedef enum
{
 EPT_GLD_OneShot_DIS = ((CSP_REGISTER_T)(0x00ul << 5)),
 EPT_GLD_OneShot_EN = ((CSP_REGISTER_T)(0x01ul << 5))
}EPT_GLD_OneShot_CMD_Type;



typedef enum
{
 EPT_PRDR_EventLoad_PEND = ((CSP_REGISTER_T)(0x00ul << 4)),
 EPT_PRDR_EventLoad_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x01ul << 4)),
 EPT_PRDR_EventLoad_Zro_ExiLoad_SYNC = ((CSP_REGISTER_T)(0x02ul << 4)),
 EPT_PRDR_EventLoad_Immediate = ((CSP_REGISTER_T)(0x03ul << 4))
} EPT_PRDR_EventLoad_Type;




typedef enum
{
 EPT_CMPX_EventLoad_DIS = 0,
 EPT_CMPX_EventLoad_Immediate = 1,
 EPT_CMPX_EventLoad_ZRO = 2,
 EPT_CMPX_EventLoad_PRD = 3,
 EPT_CMPX_EventLoad_ExiLoad_SYNC = 4
}EPT_CMPX_EventLoad_Type;



typedef enum
{
 EPT_AQCRX_EventLoad_DIS = 0,
 EPT_AQCRX_EventLoad_Immediate = 1,
 EPT_AQCRX_EventLoad_ZRO = 2,
 EPT_AQCRX_EventLoad_PRD = 3,
 EPT_AQCRX_EventLoad_ExiLoad_SYNC = 4
}EPT_AQCRX_EventLoad_Type;



typedef enum
{
 EPT_PWMA = 0,
 EPT_PWMB = 1,
 EPT_PWMC = 2,
 EPT_PWMD = 3
}EPT_PWMX_Selecte_Type;



typedef enum
{
 EPT_CA_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 20)),
 EPT_CA_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 20)),
 EPT_CA_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 20)),
 EPT_CA_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 20))
}EPT_CA_Selecte_Type;



typedef enum
{
 EPT_CB_Selecte_CMPA = ((CSP_REGISTER_T)(0x00ul << 22)),
 EPT_CB_Selecte_CMPB = ((CSP_REGISTER_T)(0x01ul << 22)),
 EPT_CB_Selecte_CMPC = ((CSP_REGISTER_T)(0x02ul << 22)),
 EPT_CB_Selecte_CMPD = ((CSP_REGISTER_T)(0x03ul << 22))
}EPT_CB_Selecte_Type;



typedef enum
{
 EPT_PWM_ZRO_Event_Nochange = ((CSP_REGISTER_T)(0x00ul )),
 EPT_PWM_ZRO_Event_OutLow = ((CSP_REGISTER_T)(0x01ul )),
 EPT_PWM_ZRO_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul )),
 EPT_PWM_ZRO_Event_Negate = ((CSP_REGISTER_T)(0x03ul ))
}EPT_PWM_ZRO_Output_Type;



typedef enum
{
 EPT_PWM_PRD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<2 )),
 EPT_PWM_PRD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<2 )),
 EPT_PWM_PRD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<2 )),
 EPT_PWM_PRD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<2 ))
}EPT_PWM_PRD_Output_Type;



typedef enum
{
 EPT_PWM_CAU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<4 )),
 EPT_PWM_CAU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<4 )),
 EPT_PWM_CAU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<4 )),
 EPT_PWM_CAU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<4 ))
}EPT_PWM_CAU_Output_Type;



typedef enum
{
 EPT_PWM_CAD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<6 )),
 EPT_PWM_CAD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<6 )),
 EPT_PWM_CAD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<6 )),
 EPT_PWM_CAD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<6 ))
}EPT_PWM_CAD_Output_Type;



typedef enum
{
 EPT_PWM_CBU_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<8 )),
 EPT_PWM_CBU_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<8 )),
 EPT_PWM_CBU_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<8 )),
 EPT_PWM_CBU_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<8 ))
}EPT_PWM_CBU_Output_Type;



typedef enum
{
 EPT_PWM_CBD_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<10 )),
 EPT_PWM_CBD_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<10 )),
 EPT_PWM_CBD_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<10 )),
 EPT_PWM_CBD_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<10 ))
}EPT_PWM_CBD_Output_Type;



typedef enum
{
 EPT_PWM_T1U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<12 )),
 EPT_PWM_T1U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<12 )),
 EPT_PWM_T1U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<12 )),
 EPT_PWM_T1U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<12 ))
}EPT_PWM_T1U_Output_Type;



typedef enum
{
 EPT_PWM_T1D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<14 )),
 EPT_PWM_T1D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<14 )),
 EPT_PWM_T1D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<14 )),
 EPT_PWM_T1D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<14 ))
}EPT_PWM_T1D_Output_Type;



typedef enum
{
 EPT_PWM_T2U_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<16 )),
 EPT_PWM_T2U_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<16 )),
 EPT_PWM_T2U_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<16 )),
 EPT_PWM_T2U_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<16 ))
}EPT_PWM_T2U_Output_Type;



typedef enum
{
 EPT_PWM_T2D_Event_Nochange = ((CSP_REGISTER_T)(0x00ul<<18 )),
 EPT_PWM_T2D_Event_OutLow = ((CSP_REGISTER_T)(0x01ul<<18 )),
 EPT_PWM_T2D_Event_OutHigh = ((CSP_REGISTER_T)(0x02ul<<18 )),
 EPT_PWM_T2D_Event_Negate = ((CSP_REGISTER_T)(0x03ul<<18 ))
}EPT_PWM_T2D_Output_Type;



typedef enum
{
 EPT_CPCR_ENALBE = ((CSP_REGISTER_T)(0x01ul<<16 )),
 EPT_CPCR_Disable = ((CSP_REGISTER_T)(0x00ul<<16 ))
}EPT_CPCR_CMD_Type;



typedef enum
{
 EPT_CPCR_Source_TCLK = ((CSP_REGISTER_T)(0)),
 EPT_CPCR_Source_TIN_BT0OUT = ((CSP_REGISTER_T)(1)),
 EPT_CPCR_Source_TIN_BT1OUT = ((CSP_REGISTER_T)(2))
}EPT_CPCR_Source_Selecte_Type;



typedef enum
{
 EPT_CDUTY_DIS = ((CSP_REGISTER_T)(0<<11)),
 EPT_CDUTY_7_8 = ((CSP_REGISTER_T)(1<<11)),
 EPT_CDUTY_6_8 = ((CSP_REGISTER_T)(2<<11)),
 EPT_CDUTY_5_8 = ((CSP_REGISTER_T)(3<<11)),
 EPT_CDUTY_4_8 = ((CSP_REGISTER_T)(4<<11)),
 EPT_CDUTY_3_8 = ((CSP_REGISTER_T)(5<<11)),
 EPT_CDUTY_2_8 = ((CSP_REGISTER_T)(6<<11)),
 EPT_CDUTY_1_8 = ((CSP_REGISTER_T)(7<<11))
}EPT_CDUTY_Type;



typedef enum
{
 EPT_EP0 = 0,
 EPT_EP1 = 1,
 EPT_EP2 = 2,
 EPT_EP3 = 3,
 EPT_EP4 = 4,
 EPT_EP5 = 5,
 EPT_EP6 = 6,
 EPT_EP7 = 7
}EPT_EPX_Type;



typedef enum
{
 EPT_Input_selecte_EPI0 = ((CSP_REGISTER_T)(1)),
 EPT_Input_selecte_EPI1 = ((CSP_REGISTER_T)(2)),
 EPT_Input_selecte_EPI2 = ((CSP_REGISTER_T)(3)),
 EPT_Input_selecte_EPI3 = ((CSP_REGISTER_T)(4)),
 EPT_Input_selecte_EPI4 = ((CSP_REGISTER_T)(5)),
 EPT_Input_selecte_ORL0 = ((CSP_REGISTER_T)(0XE)),
 EPT_Input_selecte_ORL1 = ((CSP_REGISTER_T)(0XF))
}EPT_Input_selecte_Type;



typedef enum
{
 EPT_FLT_PACE0_DIS = ((CSP_REGISTER_T)(0<<8)),
 EPT_FLT_PACE0_2CLK = ((CSP_REGISTER_T)(1<<8)),
 EPT_FLT_PACE0_3CLK = ((CSP_REGISTER_T)(2<<8)),
 EPT_FLT_PACE0_4CLK = ((CSP_REGISTER_T)(3<<8))
}EPT_FLT_PACE0_Type;



typedef enum
{
 EPT_FLT_PACE1_DIS = ((CSP_REGISTER_T)(0<<10)),
 EPT_FLT_PACE1_2CLK = ((CSP_REGISTER_T)(1<<10)),
 EPT_FLT_PACE1_3CLK = ((CSP_REGISTER_T)(2<<10)),
 EPT_FLT_PACE1_4CLK = ((CSP_REGISTER_T)(3<<10))
}EPT_FLT_PACE1_Type;



typedef enum
{
 EPT_DB_EventLoad_DIS = 0,
 EPT_DB_EventLoad_Immediate = 1,
 EPT_DB_EventLoad_ZRO = 2,
 EPT_DB_EventLoad_PRD = 3,
 EPT_DB_EventLoad_ZRO_PRD = 4
}EPT_DB_EventLoad_Type;



typedef enum
{
 EPT_CHA_Selecte = 0,
 EPT_CHB_Selecte = 1,
 EPT_CHC_Selecte = 2,
}EPT_CHX_Selecte_Type;



typedef enum
{
 EPT_CHAINSEL_PWMA_RISE_FALL = ((CSP_REGISTER_T)(0<<4)),
 EPT_CHAINSEL_PWMB_RISE_PWMA_FALL = ((CSP_REGISTER_T)(1<<4)),
 EPT_CHAINSEL_PWMA_RISE_PWMB_FALL = ((CSP_REGISTER_T)(2<<4)),
 EPT_CHAINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(3<<4)),
 EPT_CHBINSEL_PWMB_RISE_FALL = ((CSP_REGISTER_T)(0<<12)),
 EPT_CHBINSEL_PWMC_RISE_PWMB_FALL = ((CSP_REGISTER_T)(1<<12)),
 EPT_CHBINSEL_PWMB_RISE_PWMC_FALL = ((CSP_REGISTER_T)(2<<12)),
 EPT_CHBINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(3<<12)),
 EPT_CHCINSEL_PWMC_RISE_FALL = ((CSP_REGISTER_T)(0<<20)),
 EPT_CHCINSEL_PWMD_RISE_PWMC_FALL = ((CSP_REGISTER_T)(1<<20)),
 EPT_CHCINSEL_PWMC_RISE_PWMD_FALL = ((CSP_REGISTER_T)(2<<20)),
 EPT_CHCINSEL_PWMD_RISE_FALL = ((CSP_REGISTER_T)(3<<20))
}EPT_INSEL_Type;



typedef enum
{
 EPT_CHA_OUTSEL_PWMA_PWMB_Bypass = ((CSP_REGISTER_T)(0)),
 EPT_CHA_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1)),
 EPT_CHA_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2)),
 EPT_CHA_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3)),
 EPT_CHB_OUTSEL_PWMB_PWMC_Bypass = ((CSP_REGISTER_T)(0<<8)),
 EPT_CHB_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<8)),
 EPT_CHB_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<8)),
 EPT_CHB_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<8)),
 EPT_CHC_OUTSEL_PWMC_PWMD_Bypass = ((CSP_REGISTER_T)(0<<16)),
 EPT_CHC_OUTSEL_DisRise_EnFall = ((CSP_REGISTER_T)(1<<16)),
 EPT_CHC_OUTSEL_EnRise_DisFall = ((CSP_REGISTER_T)(2<<16)),
 EPT_CHC_OUTSEL_EnRise_EnFall = ((CSP_REGISTER_T)(3<<16))
}EPT_OUTSEL_Type;



typedef enum
{
 EPT_PA_PB_OUT_Direct = ((CSP_REGISTER_T)(0)),
 EPT_PA_OUT_Reverse = ((CSP_REGISTER_T)(1)),
 EPT_PB_OUT_Reverse = ((CSP_REGISTER_T)(2)),
 EPT_PA_PB_OUT_Reverse = ((CSP_REGISTER_T)(3))
}EPT_OUT_POLARITY_Type;



typedef enum
{
 EPT_PAtoCHX_PBtoCHY = ((CSP_REGISTER_T)(0)),
 EPT_PBtoCHX_PBtoCHY = ((CSP_REGISTER_T)(1)),
 EPT_PAtoCHX_PAtoCHY = ((CSP_REGISTER_T)(2)),
 EPT_PBtoCHX_PAtoCHY = ((CSP_REGISTER_T)(3))
}EPT_OUT_SWAP_Type;



typedef enum
{
 EPT_TRGSRC0 = 0,
 EPT_TRGSRC1 = 1,
 EPT_TRGSRC2 = 2,
 EPT_TRGSRC3 = 3
}EPT_TRGSRCX_Select_Type;



 typedef enum
{
 EPT_EVTRG_TRGSRCX_DIS = ((CSP_REGISTER_T)(0x00ul )),
 EPT_EVTRG_TRGSRCX_ZRO = ((CSP_REGISTER_T)(0x01ul )),
 EPT_EVTRG_TRGSRCX_PRD = ((CSP_REGISTER_T)(0x02ul )),
 EPT_EVTRG_TRGSRCX_ZROorPRD = ((CSP_REGISTER_T)(0x03ul )),
 EPT_EVTRG_TRGSRCX_CMPAU = ((CSP_REGISTER_T)(0x04ul )),
 EPT_EVTRG_TRGSRCX_CMPAD = ((CSP_REGISTER_T)(0x05ul )),
 EPT_EVTRG_TRGSRCX_CMPBU = ((CSP_REGISTER_T)(0x06ul )),
 EPT_EVTRG_TRGSRCX_CMPBD = ((CSP_REGISTER_T)(0x07ul )),
 EPT_EVTRG_TRGSRCX_CMPCU = ((CSP_REGISTER_T)(0x08ul )),
 EPT_EVTRG_TRGSRCX_CMPCD = ((CSP_REGISTER_T)(0x09ul )),
 EPT_EVTRG_TRGSRCX_CMPDU = ((CSP_REGISTER_T)(0x0Aul )),
 EPT_EVTRG_TRGSRCX_CMPDD = ((CSP_REGISTER_T)(0x0Bul )),
 EPT_EVTRG_TRGSRC01_ExtSync = ((CSP_REGISTER_T)(0x0Cul )),
 EPT_EVTRG_TRGSRC23_PeriodEnd = ((CSP_REGISTER_T)(0x0Cul )),
 EPT_EVTRG_TRGSRCX_PE0 = ((CSP_REGISTER_T)(0x0Dul )),
 EPT_EVTRG_TRGSRCX_PE1 = ((CSP_REGISTER_T)(0x0Eul )),
 EPT_EVTRG_TRGSRCX_PE2 = ((CSP_REGISTER_T)(0x0Ful ))
}EPT_EVTRG_TRGSRCX_TypeDef;
 typedef enum
{
 EPT_TRGSRCX_EN = ((CSP_REGISTER_T)0x00ul),
 EPT_TRGSRCX_DIS = ((CSP_REGISTER_T)0x01ul)
}EPT_TRGSRCX_CMD_TypeDef;



typedef enum
{

 EPT_TRGEV0_INT = ((CSP_REGISTER_T)(0x01ul << 0)),
 EPT_TRGEV1_INT = ((CSP_REGISTER_T)(0x01ul << 1)),
 EPT_TRGEV2_INT = ((CSP_REGISTER_T)(0x01ul << 2)),
 EPT_TRGEV3_INT = ((CSP_REGISTER_T)(0x01ul << 3)),
 EPT_CAP_LD0 = ((CSP_REGISTER_T)(0x01ul << 4)),
 EPT_CAP_LD1 = ((CSP_REGISTER_T)(0x01ul << 5)),
 EPT_CAP_LD2 = ((CSP_REGISTER_T)(0x01ul << 6)),
 EPT_CAP_LD3 = ((CSP_REGISTER_T)(0x01ul << 7)),
 EPT_CAU = ((CSP_REGISTER_T)(0x01ul <<8)),
 EPT_CAD = ((CSP_REGISTER_T)(0x01ul <<9)),
 EPT_CBU = ((CSP_REGISTER_T)(0x01ul <<10)),
 EPT_CBD = ((CSP_REGISTER_T)(0x01ul <<11)),
 EPT_CCU = ((CSP_REGISTER_T)(0x01ul <<12)),
 EPT_CCD = ((CSP_REGISTER_T)(0x01ul <<13)),
 EPT_CDU = ((CSP_REGISTER_T)(0x01ul <<14)),
 EPT_CDD = ((CSP_REGISTER_T)(0x01ul <<15)),
 EPT_PEND = ((CSP_REGISTER_T)(0x01ul <<16))
}EPT_INT_TypeDef;



typedef enum
{

 EPT_EP0_EMINT = ((CSP_REGISTER_T)(0x01ul << 0)),
 EPT_EP1_EMINT = ((CSP_REGISTER_T)(0x01ul << 1)),
 EPT_EP2_EMINT = ((CSP_REGISTER_T)(0x01ul << 2)),
 EPT_EP3_EMINT = ((CSP_REGISTER_T)(0x01ul << 3)),
 EPT_EP4_EMINT = ((CSP_REGISTER_T)(0x01ul << 4)),
 EPT_EP5_EMINT = ((CSP_REGISTER_T)(0x01ul << 5)),
 EPT_EP6_EMINT = ((CSP_REGISTER_T)(0x01ul << 6)),
 EPT_EP7_EMINT = ((CSP_REGISTER_T)(0x01ul << 7)),
 EPT_CPU_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 8)),
 EPT_MEM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 9)),
 EPT_EOM_FAULT_EMINT = ((CSP_REGISTER_T)(0x01ul << 10))
}EPT_EMINT_TypeDef;



typedef enum
{
 EPT_LKCR_TRG_EP0 = 0,
 EPT_LKCR_TRG_EP1 = 2,
 EPT_LKCR_TRG_EP2 = 4,
 EPT_LKCR_TRG_EP3 = 6,
 EPT_LKCR_TRG_EP4 = 8,
 EPT_LKCR_TRG_EP5 = 10,
 EPT_LKCR_TRG_EP6 = 12,
 EPT_LKCR_TRG_EP7 = 14,
 EPT_LKCR_TRG_CPU_FAULT = 15,
 EPT_LKCR_TRG_MEM_FAULT = 16,
 EPT_LKCR_TRG_EOM_FAULT = 17
}EPT_LKCR_TRG_Source_Type;



typedef enum
{
 EPT_LKCR_Mode_LOCK_DIS = ((CSP_REGISTER_T)0x00ul),
 EPT_LKCR_Mode_SLOCK_EN = ((CSP_REGISTER_T)0x01ul),
 EPT_LKCR_Mode_HLOCK_EN = ((CSP_REGISTER_T)0x02ul),
 EPT_LKCR_TRG_X_FAULT_HLOCK_EN = ((CSP_REGISTER_T)0x03ul),
 EPT_LKCR_TRG_X_FAULT_HLOCK_DIS = ((CSP_REGISTER_T)0x04ul),
}EPT_LKCR_Mode_Type;



typedef enum
{
 EPT_OUTPUT_Channel_CHAX = 0,
 EPT_OUTPUT_Channel_CHBX = 2,
 EPT_OUTPUT_Channel_CHCX = 4,
 EPT_OUTPUT_Channel_CHD = 6,
 EPT_OUTPUT_Channel_CHAY = 8,
 EPT_OUTPUT_Channel_CHBY = 10,
 EPT_OUTPUT_Channel_CHCY = 12
}EPT_OUTPUT_Channel_Type;



typedef enum
{
 EPT_SHLOCK_OUTPUT_HImpedance = 0,
 EPT_SHLOCK_OUTPUT_High = 1,
 EPT_SHLOCK_OUTPUT_Low = 2,
 EPT_SHLOCK_OUTPUT_Nochange = 3
}EPT_SHLOCK_OUTPUT_Statue_Type;




extern void EPT_Software_Prg(void);
extern void EPT_Start(void);
extern void EPT_Stop(void);
extern void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X);
extern void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X
     , U16_T EPT_PSCR);
extern void EPT_CG_gate_Config(EPT_CGSRC_TIN_Selecte_Type EPT_CGSRC_TIN_Selecte_X , U8_T EPT_CGFLT_DIV , U8_T EPT_CGFLT_CNT , EPT_BURST_CMD_Type EPT_BURST_CMD);
extern void EPT_Capture_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_CAPMD_SELECTE_Type EPT_CAPMD_SELECTE_X , EPT_CAPLDEN_CMD_Type CAP_CMD
     , EPT_LOAD_CMPA_RST_CMD_Type EPT_LOAD_CMPA_RST_CMD , EPT_LOAD_CMPB_RST_CMD_Type EPT_LOAD_CMPB_RST_CMD , EPT_LOAD_CMPC_RST_CMD_Type EPT_LOAD_CMPC_RST_CMD
     , EPT_LOAD_CMPD_RST_CMD_Type EPT_LOAD_CMPD_RST_CMD , U8_T EPT_STOP_WRAP , U16_T EPT_PSCR);
extern void EPT_SYNCR_Config(EPT_Triggle_Mode_Type EPT_Triggle_X , EPT_SYNCUSR0_REARMTrig_Selecte_Type EPT_SYNCUSR0_REARMTrig_Selecte , EPT_TRGSRC0_ExtSync_Selected_Type EPT_TRGSRC0_ExtSync_Selected ,
       EPT_TRGSRC1_ExtSync_Selected_Type EPT_TRGSRC1_ExtSync_Selected , U8_T EPT_SYNCR_EN);
extern void EPT_PHSEN_Config(EPT_PHSEN_CMD_Type EPT_PHSEN_CMD , EPT_PHSDIR_Type EPT_PHSDIR , U16_T PHSR);
extern void EPT_SYNCR_RearmClr(EPT_REARMX_Type EPT_REARMX );
extern void EPT_Caputure_Rearm(void);
extern void EPT_Globle_Eventload_Config(EPT_GLD_OneShot_CMD_Type EPT_GLD_OneShot_CMD , EPT_GLDMD_Selecte_Type EPT_GLDMD_Selecte_X , U8_T GLDPRD_CNT , U16_T GLDCFG_EN);
extern void EPT_Globle_SwLoad_CMD(void);
extern void EPT_CPCR_Config(EPT_CPCR_CMD_Type EPT_CPCR_CMD , EPT_CPCR_Source_Selecte_Type EPT_CPCR_Source_X , EPT_CDUTY_Type EPT_CDUTY_X , U8_T EPT_CPCR_OSPWTH , U8_T EPT_CPCR_CDIV);
extern void EPT_PWMX_Output_Control(
        EPT_PWMX_Selecte_Type EPT_PWMX_Selecte ,EPT_CA_Selecte_Type EPT_CA_Selecte_X , EPT_CB_Selecte_Type EPT_CB_Selecte_X ,
        EPT_PWM_ZRO_Output_Type EPT_PWM_ZRO_Event_Output , EPT_PWM_PRD_Output_Type EPT_PWM_PRD_Event_Output ,
        EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output ,
        EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output ,
        EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output ,
        EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output
        );
extern void EPT_Tevent_Selecte( U8_T EPT_T1_Selecte, U8_T EPT_T2_Selecte);
extern void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value);
extern void EPT_PRDR_EventLoad_Config(EPT_PRDR_EventLoad_Type EPT_PRDR_EventLoad_x);
extern void EPT_CMP_EventLoad_Config(EPT_CMPX_EventLoad_Type EPT_CMPX_EventLoad_x);
extern void EPT_AQCR_Eventload_Config(EPT_AQCRX_EventLoad_Type EPT_AQCRX_EventLoad_X);
extern void EPT_EPX_Config(EPT_EPX_Type EPT_EPX , EPT_Input_selecte_Type EPT_Input_selecte_x , EPT_FLT_PACE0_Type EPT_FLT_PACE0_x , EPT_FLT_PACE1_Type EPT_FLT_PACE1_x , U8_T ORL0_EPIx , U8_T ORL1_EPIx);
extern void EPT_EPIX_POL_Config(U8_T EPT_EPIX_POL);
extern void EPT_DB_Eventload_Config(EPT_DB_EventLoad_Type EPT_DB_EventLoad_X);
extern void EPT_DBCR_Config(EPT_CHX_Selecte_Type EPT_CHX_Selecte , EPT_INSEL_Type EPT_INSEL_X , EPT_OUTSEL_Type EPT_OUTSEL_X , EPT_OUT_POLARITY_Type EPT_OUT_POLARITY_X , EPT_OUT_SWAP_Type EPT_OUT_SWAP_X);
extern void EPT_DB_CLK_Config(U16_T DPSC , U16_T DTR , U16_T DTF);
extern void EPT_TRGSRCX_Config(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select , EPT_EVTRG_TRGSRCX_TypeDef EPT_EVTRG_TRGSRCX_X , EPT_TRGSRCX_CMD_TypeDef EPT_TRGSRCX_CMD , U8_T TRGEVXPRD);
extern void EPT_TRGSRCX_SWFTRG(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select);
extern void EPT_Int_Enable(EPT_INT_TypeDef EPT_X_INT);
extern void EPT_Int_Disable(EPT_INT_TypeDef EPT_X_INT);
extern void EPT_EMInt_Enable(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_EMInt_Disable(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_Vector_Int_Enable(void);
extern void EPT_Vector_Int_Disable(void);
extern void EPT_SLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_HLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_SW_Set_lock(EPT_EMINT_TypeDef EPT_X_EMINT);
extern void EPT_LKCR_TRG_Config(EPT_LKCR_TRG_Source_Type EPT_LKCR_TRG_X , EPT_LKCR_Mode_Type EPT_LKCR_Mode_X);
extern void EPT_SHLOCK_OUTPUT_Config(EPT_OUTPUT_Channel_Type EPT_OUTPUT_Channel_X , EPT_SHLOCK_OUTPUT_Statue_Type EPT_SHLOCK_OUTPUT_X);
# 20 "FWlib/apt32f102_ept.c" 2







void EPT_Software_Prg(void)
{
 EPT0->CEDR|=0X01;
 EPT0->RSSR=(EPT0->RSSR&0XFFFF0FFF)|(0X05<<12);
}





void EPT_Start(void)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->RSSR|=0X01;
 while(!(EPT0->RSSR&0x01));
}





void EPT_Stop(void)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->RSSR&=0Xfe;
 while(EPT0->RSSR&0x01);
}






void EPT_IO_SET(EPT_IO_Mode_Type EPT_IO_X , EPT_IO_NUM_Type IO_Num_X)
{
 if(EPT_IO_X==EPT_IO_CHAX)
 {
  if(IO_Num_X==IO_NUM_PA07)
  {
   GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X60000000;
  }
  else if(IO_Num_X==IO_NUM_PA10)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFF0FF)|0X00000500;
  }
  else if(IO_Num_X==IO_NUM_PA15)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0X0FFFFFFF)|0X40000000;
  }
 }
 else if(EPT_IO_X==EPT_IO_CHAY)
 {
  if(IO_Num_X==IO_NUM_PB03)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00005000;
  }
  else if(IO_Num_X==IO_NUM_PB05)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00400000;
  }
  else if(IO_Num_X==IO_NUM_PA12)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFF0FFFF)|0X00050000;
  }
 }
 else if(EPT_IO_X==EPT_IO_CHBX)
 {
  if(IO_Num_X==IO_NUM_PB02)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000600;
  }
  else if(IO_Num_X==IO_NUM_PA11)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFF0FFF)|0X00005000;
  }
  else if(IO_Num_X==IO_NUM_PA14)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XF0FFFFFF)|0X04000000;
  }
 }
 else if(EPT_IO_X==EPT_IO_CHBY)
 {
  if(IO_Num_X==IO_NUM_PB04)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00050000;
  }
  else if(IO_Num_X==IO_NUM_PA05)
  {
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFF0FFFFF)|0X00800000;
  }
  else if(IO_Num_X==IO_NUM_PA08)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000005;
  }
 }
 else if(EPT_IO_X==EPT_IO_CHCX)
 {
  if(IO_Num_X==IO_NUM_PB05)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFF0FFFFF)|0X00400000;
  }
  else if(IO_Num_X==IO_NUM_PA03)
  {
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFFF0FFF)|0X00005000;
  }
  else if(IO_Num_X==IO_NUM_PB03)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00004000;
  }
  else if(IO_Num_X==IO_NUM_PB00)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFFFF0)|0X00000005;
  }
 }
 else if(EPT_IO_X==EPT_IO_CHCY)
 {
  if(IO_Num_X==IO_NUM_PB04)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFF0FFFF)|0X00040000;
  }
  else if(IO_Num_X==IO_NUM_PA04)
  {
   GPIOA0->CONLR = (GPIOA0->CONLR&0XFFF0FFFF)|0X00050000;
  }
  else if(IO_Num_X==IO_NUM_PA09)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFF0F)|0X00000070;
  }
  else if(IO_Num_X==IO_NUM_PA013)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00500000;
  }
 }
 else if(EPT_IO_X==EPT_IO_CHD)
 {
  if(IO_Num_X==IO_NUM_PB03)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00006000;
  }
  else if(IO_Num_X==IO_NUM_PA08)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFFFFFFF0)|0X00000004;
  }
 }
 else if(EPT_IO_X==EPT_IO_EPI)
 {
  if(IO_Num_X==IO_NUM_PA07)
  {
   GPIOA0->CONLR = (GPIOA0->CONLR&0X0FFFFFFF)|0X50000000;
  }
  else if(IO_Num_X==IO_NUM_PA013)
  {
   GPIOA0->CONHR = (GPIOA0->CONHR&0XFF0FFFFF)|0X00400000;
  }
  else if(IO_Num_X==IO_NUM_PB03)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFF0FFF)|0X00007000;
  }
  else if(IO_Num_X==IO_NUM_PB02)
  {
   GPIOB0->CONLR = (GPIOB0->CONLR&0XFFFFF0FF)|0X00000700;
  }
 }
}
# 201 "FWlib/apt32f102_ept.c"
void EPT_PWM_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_OPM_SELECTE_Type EPT_OPM_SELECTE_X
     , U16_T EPT_PSCR)

{
 EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6));
 if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK)
 {
  EPT0->PSCR=EPT_PSCR;
 }
 EPT0->CR=(EPT0->CR&0xfff8ffc0)|EPT_CNTMD_SELECTE_X|(0x1<<2)|(0x0<<3)|(0x0<<4)|EPT_OPM_SELECTE_X|(0X0<<16)|(0x1<<18);
}
# 221 "FWlib/apt32f102_ept.c"
void EPT_CG_gate_Config(EPT_CGSRC_TIN_Selecte_Type EPT_CGSRC_TIN_Selecte_X , U8_T EPT_CGFLT_DIV , U8_T EPT_CGFLT_CNT , EPT_BURST_CMD_Type EPT_BURST_CMD)
{
 EPT0->CR=(EPT0->CR&0xffff01ff)|EPT_BURST_CMD|EPT_CGFLT_CNT<<13|0x01<<10;
 EPT0->CEDR=(EPT0->CEDR&0XFFFF00CF)|(EPT_CGFLT_DIV<<8);
 if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_DIS)
 {
  EPT0->CEDR|=0X00<<4;
  EPT0->CR|=0X03<<11;
 }
 else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_TIN_BT0OUT)
 {
  EPT0->CEDR|=0X01<<4;
  EPT0->CR|=0X02<<11;
 }
 else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_TIN_BT1OUT)
 {
  EPT0->CEDR|=0X02<<4;
  EPT0->CR|=0X02<<11;
 }
 else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_CHAX)
 {
  EPT0->CEDR|=0X00<<4;
  EPT0->CR|=0X00<<11;
 }
 else if(EPT_CGSRC_TIN_Selecte_X==EPT_CGSRC_CHBX)
 {
  EPT0->CEDR|=0X00<<4;
  EPT0->CR|=0X01<<11;
 }
}
# 265 "FWlib/apt32f102_ept.c"
void EPT_Capture_Config(EPT_TCLK_Selecte_Type EPT_TCLK_Selecte_X , EPT_CNTMD_SELECTE_Type EPT_CNTMD_SELECTE_X , EPT_CAPMD_SELECTE_Type EPT_CAPMD_SELECTE_X , EPT_CAPLDEN_CMD_Type CAP_CMD
     , EPT_LOAD_CMPA_RST_CMD_Type EPT_LOAD_CMPA_RST_CMD , EPT_LOAD_CMPB_RST_CMD_Type EPT_LOAD_CMPB_RST_CMD , EPT_LOAD_CMPC_RST_CMD_Type EPT_LOAD_CMPC_RST_CMD
     , EPT_LOAD_CMPD_RST_CMD_Type EPT_LOAD_CMPD_RST_CMD , U8_T EPT_STOP_WRAP , U16_T EPT_PSCR)
{
 EPT0->CEDR=(EPT0->CEDR&0XFFFFFF00)|(0X01|EPT_TCLK_Selecte_X|(0X01<<1)|(0X00<<6));
 if(EPT_TCLK_Selecte_X==EPT_Selecte_PCLK)
 {
  EPT0->PSCR=EPT_PSCR;
 }
 EPT0->CR=(EPT0->CR&0xf800fec0)|EPT_CNTMD_SELECTE_X|(0x0<<2)|(0x0<<3)|(0x0<<4)|CAP_CMD|EPT_CAPMD_SELECTE_X|(0X0<<16)|(0x0<<18)|(EPT_STOP_WRAP<<21)|
    EPT_LOAD_CMPA_RST_CMD|EPT_LOAD_CMPB_RST_CMD|EPT_LOAD_CMPC_RST_CMD|EPT_LOAD_CMPD_RST_CMD;
}
# 289 "FWlib/apt32f102_ept.c"
void EPT_SYNCR_Config(EPT_Triggle_Mode_Type EPT_Triggle_X , EPT_SYNCUSR0_REARMTrig_Selecte_Type EPT_SYNCUSR0_REARMTrig_Selecte , EPT_TRGSRC0_ExtSync_Selected_Type EPT_TRGSRC0_ExtSync_Selected ,
       EPT_TRGSRC1_ExtSync_Selected_Type EPT_TRGSRC1_ExtSync_Selected , U8_T EPT_SYNCR_EN)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->SYNCR = (EPT0->SYNCR&0XC03F0000) |EPT_SYNCR_EN|EPT_Triggle_X|EPT_SYNCUSR0_REARMTrig_Selecte|EPT_TRGSRC0_ExtSync_Selected|EPT_TRGSRC1_ExtSync_Selected;
}
# 307 "FWlib/apt32f102_ept.c"
void EPT_CPCR_Config(EPT_CPCR_CMD_Type EPT_CPCR_CMD , EPT_CPCR_Source_Selecte_Type EPT_CPCR_Source_X , EPT_CDUTY_Type EPT_CDUTY_X , U8_T EPT_CPCR_OSPWTH , U8_T EPT_CPCR_CDIV)
{
 if(EPT_CPCR_Source_X==EPT_CPCR_Source_TCLK)
 {
  EPT0->CPCR=(EPT_CPCR_CMD<<16)|(EPT_CPCR_CDIV<<7)|(EPT_CPCR_OSPWTH<<2)|EPT_CDUTY_X|(0x00<<14);
 }
 else
 {
  EPT0->CPCR=(EPT_CPCR_CMD<<16)|(EPT_CPCR_CDIV<<7)|(EPT_CPCR_OSPWTH<<2)|EPT_CDUTY_X|(0x01<<14);
  if(EPT_CPCR_Source_X==EPT_CPCR_Source_TIN_BT0OUT)
  {
   EPT0->CEDR=(EPT0->CEDR&0xffffffcf)|(0x01<<4);
  }
  if(EPT_CPCR_Source_X==EPT_CPCR_Source_TIN_BT1OUT)
  {
   EPT0->CEDR=(EPT0->CEDR&0xffffffcf)|(0x02<<4);
  }
 }
}
# 336 "FWlib/apt32f102_ept.c"
void EPT_DBCR_Config(EPT_CHX_Selecte_Type EPT_CHX_Selecte , EPT_INSEL_Type EPT_INSEL_X , EPT_OUTSEL_Type EPT_OUTSEL_X , EPT_OUT_POLARITY_Type EPT_OUT_POLARITY_X , EPT_OUT_SWAP_Type EPT_OUT_SWAP_X)
{
 if(EPT_CHX_Selecte==EPT_CHA_Selecte)
 {
  EPT0->DBCR=(EPT0->DBCR&0XFFFFFF00)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<2)|(EPT_OUT_SWAP_X<<6);
 }
 else if(EPT_CHX_Selecte==EPT_CHB_Selecte)
 {
  EPT0->DBCR=(EPT0->DBCR&0XFFFF00FF)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<10)|(EPT_OUT_SWAP_X<<14);
 }
 else if(EPT_CHX_Selecte==EPT_CHC_Selecte)
 {
  EPT0->DBCR=(EPT0->DBCR&0XFF00FFFF)|EPT_INSEL_X|EPT_OUTSEL_X|(EPT_OUT_POLARITY_X<<18)|(EPT_OUT_SWAP_X<<22);
 }
 EPT0->DBCR|=0x01<<24;
}






void EPT_DB_CLK_Config(U16_T DPSC , U16_T DTR , U16_T DTF)
{
 EPT0->DPSCR=DPSC;
 EPT0->DBDTR=DTR;
 EPT0->DBDTF=DTF;
}
# 372 "FWlib/apt32f102_ept.c"
void EPT_PWMX_Output_Control(
        EPT_PWMX_Selecte_Type EPT_PWMX_Selecte ,EPT_CA_Selecte_Type EPT_CA_Selecte_X , EPT_CB_Selecte_Type EPT_CB_Selecte_X ,
        EPT_PWM_ZRO_Output_Type EPT_PWM_ZRO_Event_Output , EPT_PWM_PRD_Output_Type EPT_PWM_PRD_Event_Output ,
        EPT_PWM_CAU_Output_Type EPT_PWM_CAU_Event_Output , EPT_PWM_CAD_Output_Type EPT_PWM_CAD_Event_Output ,
        EPT_PWM_CBU_Output_Type EPT_PWM_CBU_Event_Output , EPT_PWM_CBD_Output_Type EPT_PWM_CBD_Event_Output ,
        EPT_PWM_T1U_Output_Type EPT_PWM_T1U_Event_Output , EPT_PWM_T1D_Output_Type EPT_PWM_T1D_Event_Output ,
        EPT_PWM_T2U_Output_Type EPT_PWM_T2U_Event_Output , EPT_PWM_T2D_Output_Type EPT_PWM_T2D_Event_Output
        )
{
 if(EPT_PWMX_Selecte==EPT_PWMA)
 {
  EPT0->AQCRA=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
     EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
 }
 else if(EPT_PWMX_Selecte==EPT_PWMB)
 {
  EPT0->AQCRB=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
     EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
 }
 else if(EPT_PWMX_Selecte==EPT_PWMC)
 {
  EPT0->AQCRC=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
     EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
 }
 else if(EPT_PWMX_Selecte==EPT_PWMD)
 {
  EPT0->AQCRD=EPT_CA_Selecte_X|EPT_CB_Selecte_X|EPT_PWM_ZRO_Event_Output|EPT_PWM_PRD_Event_Output|EPT_PWM_CAU_Event_Output|EPT_PWM_CAD_Event_Output|
     EPT_PWM_CBU_Event_Output|EPT_PWM_CBD_Event_Output|EPT_PWM_T1U_Event_Output|EPT_PWM_T1D_Event_Output|EPT_PWM_T2U_Event_Output|EPT_PWM_T2D_Event_Output;
 }

}







void EPT_Tevent_Selecte( U8_T EPT_T1_Selecte, U8_T EPT_T2_Selecte)
{
 EPT0->AQTSCR=EPT_T1_Selecte|(EPT_T2_Selecte<<4);
}
# 422 "FWlib/apt32f102_ept.c"
void EPT_PHSEN_Config(EPT_PHSEN_CMD_Type EPT_PHSEN_CMD , EPT_PHSDIR_Type EPT_PHSDIR , U16_T PHSR)
{
 EPT0->CR=(EPT0->CR&0xffffff7f)|EPT_PHSEN_CMD;
 EPT0->PHSR=PHSR|EPT_PHSDIR;
}
# 436 "FWlib/apt32f102_ept.c"
void EPT_PRDR_CMPA_CMPB_CMPC_CMPD_Config(U16_T EPT_PRDR_Value , U16_T EPT_CMPA_Value , U16_T EPT_CMPB_Value , U16_T EPT_CMPC_Value , U16_T EPT_CMPD_Value)
{
 EPT0->PRDR=EPT_PRDR_Value;
 EPT0->CMPA=EPT_CMPA_Value;
 EPT0->CMPB=EPT_CMPB_Value;
 EPT0->CMPC=EPT_CMPC_Value;
 EPT0->CMPD=EPT_CMPD_Value;
}






void EPT_SYNCR_RearmClr(EPT_REARMX_Type EPT_REARMX )
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->SYNCR = (EPT0->SYNCR&0X3FC0FFFF)|EPT_REARMX;
}






void EPT_Caputure_Rearm(void)
{
 EPT0->CR=(EPT0->CR&0xfffdffff)|(0x01<<19);
}
# 476 "FWlib/apt32f102_ept.c"
void EPT_Globle_Eventload_Config(EPT_GLD_OneShot_CMD_Type EPT_GLD_OneShot_CMD , EPT_GLDMD_Selecte_Type EPT_GLDMD_Selecte_X , U8_T GLDPRD_CNT , U16_T GLDCFG_EN)
{
 EPT0->GLDCR=0X01|EPT_GLD_OneShot_CMD|EPT_GLDMD_Selecte_X|(GLDPRD_CNT<<7);
 EPT0->GLDCFG=GLDCFG_EN;





}







void EPT_Globle_SwLoad_CMD(void)
{


 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->GLDCR2=0X03;
}






void EPT_PRDR_EventLoad_Config(EPT_PRDR_EventLoad_Type EPT_PRDR_EventLoad_x)
{
 EPT0->GLDCR&=0XFFFFFFFE;
 EPT0->CR=(EPT0->CR&0xffffffcf)|EPT_PRDR_EventLoad_x;
}







void EPT_CMP_EventLoad_Config(EPT_CMPX_EventLoad_Type EPT_CMPX_EventLoad_x)
{
 EPT0->GLDCR&=0XFFFFFFFE;
 if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_DIS)
 {
  EPT0->CMPLDR=0;
 }
 else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_Immediate)
 {
  EPT0->CMPLDR=0xf;
 }
 else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_ZRO)
 {
  EPT0->CMPLDR=0x2410;
 }
 else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_PRD)
 {
  EPT0->CMPLDR=0x4920;
 }
 else if(EPT_CMPX_EventLoad_x==EPT_CMPX_EventLoad_ExiLoad_SYNC)
 {
  EPT0->CMPLDR=0x8240;
 }
}







void EPT_AQCR_Eventload_Config(EPT_AQCRX_EventLoad_Type EPT_AQCRX_EventLoad_X)
{
 EPT0->GLDCR&=0XFFFFFFFE;
 if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_DIS)
 {
  EPT0->AQLDR=0;
 }
 else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_Immediate)
 {
  EPT0->AQLDR=0x303;
 }
 else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_ZRO)
 {
  EPT0->AQLDR=0x2424;
 }
 else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_PRD)
 {
  EPT0->AQLDR=0x4848;
 }
 else if(EPT_AQCRX_EventLoad_X==EPT_AQCRX_EventLoad_ExiLoad_SYNC)
 {
  EPT0->AQLDR=0x9090;
 }
}







void EPT_DB_Eventload_Config(EPT_DB_EventLoad_Type EPT_DB_EventLoad_X)
{
 EPT0->GLDCR&=0XFFFFFFFE;
 if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_DIS)
 {
  EPT0->DBLDR=0X249;
 }
 else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_Immediate)
 {
  EPT0->DBLDR=0;
 }
 else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_ZRO)
 {
  EPT0->DBLDR=0X249|(0X01<<1)|(0X01<<4)|(0X01<<7)|(0X01<<10);
 }
 else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_PRD)
 {
  EPT0->DBLDR=0X249|(0X02<<1)|(0X02<<4)|(0X02<<7)|(0X02<<10);
 }
 else if(EPT_DB_EventLoad_X==EPT_DB_EventLoad_ZRO_PRD)
 {
  EPT0->DBLDR=0X249|(0X03<<1)|(0X03<<4)|(0X03<<7)|(0X03<<10);
 }
}
# 613 "FWlib/apt32f102_ept.c"
void EPT_TRGSRCX_Config(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select , EPT_EVTRG_TRGSRCX_TypeDef EPT_EVTRG_TRGSRCX_X , EPT_TRGSRCX_CMD_TypeDef EPT_TRGSRCX_CMD , U8_T TRGEVXPRD)
{
 if(EPT_TRGSRCX_Select==EPT_TRGSRC0)
 {
  EPT0->EVTRG=(EPT0->EVTRG&0xffeffff0)|(EPT_EVTRG_TRGSRCX_X<<0)|(EPT_TRGSRCX_CMD<20);
 }
 else if(EPT_TRGSRCX_Select==EPT_TRGSRC1)
 {
  EPT0->EVTRG=(EPT0->EVTRG&0xffdfff0f)|(EPT_EVTRG_TRGSRCX_X<<4)|(EPT_TRGSRCX_CMD<21);
 }
 else if(EPT_TRGSRCX_Select==EPT_TRGSRC2)
 {
  EPT0->EVTRG=(EPT0->EVTRG&0xffbff0ff)|(EPT_EVTRG_TRGSRCX_X<<8)|(EPT_TRGSRCX_CMD<22);
 }
 else if(EPT_TRGSRCX_Select==EPT_TRGSRC3)
 {
  EPT0->EVTRG=(EPT0->EVTRG&0xff7f0fff)|(EPT_EVTRG_TRGSRCX_X<<12)|(EPT_TRGSRCX_CMD<23);
 }
 EPT0->EVTRG|=0x0f0f0000;
}






void EPT_TRGSRCX_SWFTRG(EPT_TRGSRCX_Select_Type EPT_TRGSRCX_Select)
{
 if(EPT_TRGSRCX_Select==EPT_TRGSRC0)
 {
  EPT0->EVSWF|=0X01;
 }
 else if(EPT_TRGSRCX_Select==EPT_TRGSRC1)
 {
  EPT0->EVSWF|=0X02;
 }
 else if(EPT_TRGSRCX_Select==EPT_TRGSRC2)
 {
  EPT0->EVSWF|=0X04;
 }
 else if(EPT_TRGSRCX_Select==EPT_TRGSRC3)
 {
  EPT0->EVSWF|=0X08;
 }
}





void EPT_Int_Enable(EPT_INT_TypeDef EPT_X_INT)
{
 EPT0->ICR = EPT_X_INT;
 EPT0->IMCR |= EPT_X_INT;
}





void EPT_Int_Disable(EPT_INT_TypeDef EPT_X_INT)
{
 EPT0->IMCR &= ~EPT_X_INT;
}






void EPT_EMInt_Enable(EPT_EMINT_TypeDef EPT_X_EMINT)
{
 EPT0->EMICR = EPT_X_EMINT;
 EPT0->EMIMCR |= EPT_X_EMINT;
}






void EPT_EMInt_Disable(EPT_EMINT_TypeDef EPT_X_EMINT)
{
 EPT0->EMIMCR &= ~EPT_X_EMINT;
}





void EPT_Vector_Int_Enable(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<4);
}





void EPT_Vector_Int_Disable(void)
{
    *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<4);
}
# 725 "FWlib/apt32f102_ept.c"
void EPT_EPX_Config(EPT_EPX_Type EPT_EPX , EPT_Input_selecte_Type EPT_Input_selecte_x , EPT_FLT_PACE0_Type EPT_FLT_PACE0_x , EPT_FLT_PACE1_Type EPT_FLT_PACE1_x , U8_T ORL0_EPIx , U8_T ORL1_EPIx)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 if(EPT_EPX==EPT_EP0)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0XFFFFFFF0)|(EPT_Input_selecte_x<<0);
 }
 else if(EPT_EPX==EPT_EP1)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0XFFFFFF0F)|(EPT_Input_selecte_x<<4);
 }
 else if(EPT_EPX==EPT_EP2)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0XFFFFF0FF)|(EPT_Input_selecte_x<<8);
 }
 else if(EPT_EPX==EPT_EP3)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0XFFFF0FFF)|(EPT_Input_selecte_x<<12);
 }
 else if(EPT_EPX==EPT_EP4)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0XFFF0FFFF)|(EPT_Input_selecte_x<<16);
 }
 else if(EPT_EPX==EPT_EP5)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0XFF0FFFFF)|(EPT_Input_selecte_x<<20);
 }
 else if(EPT_EPX==EPT_EP6)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0XF0FFFFFF)|(EPT_Input_selecte_x<<24);
 }
 else if(EPT_EPX==EPT_EP7)
 {
  EPT0->EMSRC=(EPT0->EMSRC&0X0FFFFFFF)|(EPT_Input_selecte_x<<28);
 }
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->EMSRC2=ORL0_EPIx|(ORL1_EPIx<<16)|EPT_FLT_PACE0_x|EPT_FLT_PACE1_x;
}







void EPT_EPIX_POL_Config(U8_T EPT_EPIX_POL)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->EMPOL=EPT_EPIX_POL;
}







void EPT_LKCR_TRG_Config(EPT_LKCR_TRG_Source_Type EPT_LKCR_TRG_X , EPT_LKCR_Mode_Type EPT_LKCR_Mode_X)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->EMECR|=(0X01<<21)|(0X01<<22)|(0X02<<24);
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_CPU_FAULT)
 {
  if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN)
  {
   EPT0->EMECR|=(0x01<<28);
  }
  else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS)
  {
   EPT0->EMECR&=~(0x01<<28);
  }
 }
 else if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_MEM_FAULT)
 {
  if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN)
  {
   EPT0->EMECR|=(0x01<<29);
  }
  else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS)
  {
   EPT0->EMECR&=~(0x01<<29);
  }
 }
 else if(EPT_LKCR_TRG_X==EPT_LKCR_TRG_EOM_FAULT)
 {
  if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_EN)
  {
   EPT0->EMECR|=(0x01<<30);
  }
  else if(EPT_LKCR_Mode_X==EPT_LKCR_TRG_X_FAULT_HLOCK_DIS)
  {
   EPT0->EMECR&=~(0x01<<30);
  }
 }
 else
 {
  EPT0->EMECR|=(EPT_LKCR_Mode_X<<(EPT_LKCR_TRG_X))|(0X01<<26);
 }
}
# 833 "FWlib/apt32f102_ept.c"
void EPT_SHLOCK_OUTPUT_Config(EPT_OUTPUT_Channel_Type EPT_OUTPUT_Channel_X , EPT_SHLOCK_OUTPUT_Statue_Type EPT_SHLOCK_OUTPUT_X)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->EMOSR|=EPT_SHLOCK_OUTPUT_X<<EPT_OUTPUT_Channel_X;
}






void EPT_SLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT)
{
 EPT0->EMSLCLR|=EPT_X_EMINT;
}






void EPT_HLock_CLR(EPT_EMINT_TypeDef EPT_X_EMINT)
{
 EPT0->EMHLCLR|=EPT_X_EMINT;
}






void EPT_SW_Set_lock(EPT_EMINT_TypeDef EPT_X_EMINT)
{
 EPT0->REGPROT = (0xA55A<<16) | 0xC73A;
 EPT0->EMFRCR|=EPT_X_EMINT;
}
